Introduction:
Most FPGA designs today rely on an HDL based description of their design. HDL synthesis is probably the single most important software flow step when it comes to defining the performance of a design. Synthesis links the conceptual description of the logic functions needed for the design to their actual physical architecture elements in the underlying device. This step cannot be underestimated. Synthesis is performed prior to chip placement as an entirely separate step, hence these technology dependent optimizations are computed without knowledge of actual chip placement. As a result, design performance can be far from optimal, impacted by choices made too early. This is where physical synthesis comes into play, bringing physical information to the synthesis engine.
Traditional Flow versus Physical Synthesis Flow:
The most common design flows use synthesis and place & route as two consecutive disjointed steps. Synthesis generates an EDIF netlist that is then passed on to the backend for implementation. The netlist contains basic elements such as LUTs, flip-flops, etc., but does not control how these elements will be packaged together in the FPGA clusters (referred to as “slices” in Xilinx® FPGAs) during the packing phase. Synthesis also has no control on placement and often does not have access to the entire design, if cores are used as black boxes.
With physical synthesis, it’s different. Physical synthesis yields a better result because it provides information about the actual critical paths, the ones that placement is actually seeing. This is a key feature as it closes the loop between synthesis and place & route.
Figure 1 compares the two flows. The traditional flow is shown on the left and the physical synthesis flow using Xilinx® ISE™ 9.1i is shown on the right. All options in blue are explained in detail in the next section.
Figure.1:
Another key advantage of physical synthesis is that it guarantees a better level of consistency for both the synthesis and implementation constraints. By having an integrated environment for synthesis, packing and placement, it guarantees that synthesis and place & route are working on the same problem.
An important silicon architecture consideration: The trend in modern FPGA silicon architecture is to offer more and more capable clusters (or slices). This permits more possibilities for physical synthesis flows since the traditional ISE software flow places already pre-packed slices. In effect, the traditional flow does not place LUTs and flip-flops, it actually places slices. The –timing option in ISE software enables placement at the most basic element level (non only LUTs and flip-flops but also logic fragments in the slice like dedicated arithmetic and multiplexer circuitry).
These MAP options will have more opportunities to make improvements in the following situations:
1) Under-constraining in synthesis prevents it from generating the best optimizations. To avoid this situation, it is recommended to tightly constrain synthesis until the tool reports negative slack.
2) Inconsistent constraining between synthesis and implementation is a fairly common situation in which synthesis is not driven to optimize paths that are later constrained during implementation.
3) Physical synthesis can likely re-build the fast logic needed to meet timing. To remedy this situation in the traditional flow, carefully examine constraints between synthesis and implementation and make sure similar paths are covered in both.
4) In a bottom-up or partition flow, synthesis may not optimize between blocks or partitions.
5) Design reuse netlist used as “black-boxes” in synthesis may limit the amount of possible optimization. Note that synthesis has the capability in the traditional flow to “read” netlists from black-boxes. This helps the tools analyze paths going to and coming from the black boxes. But sometimes these black boxes are not added to the synthesis project and this is where physical synthesis options can have a great impact.
6) Designs with high LUT to flip-flop ratio (few registers for a lot of logic) are more likely to benefit from the retiming option. Note that retiming (called register balancing in XST) is also available in synthesis and can be used as part of the traditional flow.
7) Even if care is taken during the synthesis step and constraints are consistent between synthesis and implementation, physical synthesis can improve performance. Following are some of the optimizations used in the algorithms:
Logic Duplication:
If a LUT or flip-flop drives multiple loads, and the placement of one or more of those loads is too far away from the source to meet timing requirements, the LUT or flip-flop can be replicated and placed close to that group of loads, thus reducing routing delays.
Logic Recombination: If the critical path traverses through multiple LUTs and through multiple slices, the logic can be reassembled utilizing fewer slices by using a more timing efficient combination of LUTs and MUXes to reduce the routing resources needed for that path.
Basic Element Switching: If a function is built with LUTs and MUXes within a slice, physical synthesis and optimization can rearrange the function to give the fastest path (usually through the MUX select pin) to the most critical signal as shown in
Figure 2:
Pin Swapping:
Each input pin of a LUT may have a different delay. MAP has the ability to swap pins (and change the LUT equation accordingly) so that the most critical signal is assigned to the fastest pin. This is particularly effective with the Xilinx® Virtex™-5 FPGAs since its 6-input LUTs have distributed delays, with pins 1 through 6 being increasingly faster (pin 6 being the fastest). This pin swapping capability in MAP helps predict timing with more accuracy. It should be noted that during routing, pins can also be swapped. In the traditional flow only the routing phase will operate pin swapping.
In conclusion, Xilinx ISE 9.1i software provides several options to enable physical optimizations in a one pass flow. Choosing the right one (or the right ones) can prove to be difficult. To make it easier, Xilinx provides the Xplorer utility to run the design with these optimizations and to select the best one. The Xplorer utility is available at the command line and also from the GUI with Project Navigator.
Conclusion:
Physical synthesis enables better results by bridging synthesis and place & route. Xilinx provides the technology as part of ISE 9.1i using re-synthesis algorithms that can be applied to any incoming netlists.
